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| HTG2190 8-bit 1024 pixel dot matrix lcd mcu series rev. 1.20 1 july 5, 2002 features operating voltage: 2.4v~3.6v 64k 16 bits program rom 2.3k 8 bits data ram 15~39 bidirectional i/o lines 16 common 40~64 segment lcd driver two 16-bit programmable timer/event counters with overflow interrupts one 8-bit programmable timer with 8-stage prescaler for pfd one 8-bit programmable timer with 8-stage prescaler for time base one 8-bit pwm audio output to directly drive speaker or buzzer one 12-bit current type d/a output with 4-bit volume control r to f function for temperature measurement synchronous serial interface on-chip rc oscillator for system clock 32768hz crystal oscillator for time base and lcd driver watchdog timer halt function and wake-up feature reduce power consumption eight-level subroutine nesting bit manipulation instructions 63 powerful instructions built-in supply voltage detection circuit one interrupt input 128-pin qfp package general description the HTG2190 is an 8-bit high performance risc-like microcontroller capable of driving 1024 pixel (max.) lcd display. its single cycle instruction and two-stage pipeline architecture make it suitable for high speed ap- plications. the device is suited for use in multiple lcd low power applications among which are calculators, clock timer, game, scales, leisure products, other hand held lcd products and battery operated systems in par- ticular.
block diagram HTG2190 rev. 1.20 2 july 5, 2002 ! " # $ % & " ' ( ) * + ( , , & - . / + , & & + & 0 % & " ' ( ) * 1 ( + & 0 & 2 1 ( ) 3 2 / / & 2 1 ( ) 2 ) 1 ' . ' 4 ' ) ' / ' + ' 1 & 2 1 ( / + 2 + 4 * * & * * 5 & * . 2 * 1 ( 1 ( + 4 ( + ( + . " ! " & 6 2 / 2 4 7 2 1 ( ) 2 ) 1 2 1 ( ) 3 2 / / 2 / ( / + 2 + ( + ( + . ( 1 ( + 4 3 8 - 9 . ( & 2 1 - $ 3 8 - , ( " ' ( * / ( ( * ) , , . 4 4 4 . 1 + 3 : ; & ! - % & " ' 3 8 - 3 8 - . % & " ' * ( , , . ( ' ' , , . . & 0 ( ) & 0 - & - 9 - ! & - & % & " ' % & " ' pin assignment HTG2190 rev. 1.20 3 july 5, 2002 pad assignment chip size: 3420 3855 ( m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. pad coordinates unit: m pad no. x y pad no. x y 1 1561.08 1781.81 58 1214.37 1797.56 2 1577.85 1535.18 59 1156.72 1465.33 3 1577.85 1428.50 60 1331.47 1797.56 4 1577.85 1322.07 61 1442.47 1797.56 5 1577.85 1215.39 62 1559.56 1797.56 6 1577.85 1108.96 63 1264.67 1465.33 7 1577.85 1002.28 64 1492.25 1516.38 8 1577.85 895.86 65 1492.25 1404.62 HTG2190 rev. 1.20 4 july 5, 2002 ! " # $ pad no. x y pad no. x y 9 1577.85 789.18 66 1264.67 1351.53 10 1577.85 682.75 67 1240.28 1235.20 11 1577.85 576.33 68 1492.25 1119.38 12 1577.85 469.65 69 1515.36 991.36 13 1577.85 363.22 70 1517.14 867.16 14 1577.85 256.54 71 1517.14 745.49 15 1577.85 150.11 72 1517.14 596.65 16 1577.85 43.43 73 1517.14 422.91 17 1577.85 62.99 74 1517.14 271.27 18 1577.85 169.67 75 1517.14 154.18 19 1577.85 276.10 76 1517.14 40.13 20 1577.85 382.78 77 1517.14 76.45 21 1577.85 489.20 78 1517.14 190.50 22 1577.85 595.88 79 1517.14 307.34 23 1577.85 702.31 80 1517.14 421.39 24 1577.85 809.99 81 1517.14 538.23 25 1577.85 915.42 82 1517.14 652.27 26 1577.85 1022.10 83 1517.14 768.86 27 1577.85 1128.52 84 1517.14 882.90 28 1577.85 1235.20 85 1517.14 999.74 29 1577.85 1341.63 86 1517.14 1113.79 30 1577.85 1448.31 87 1517.14 1230.63 31 1577.85 1554.73 88 1544.83 1734.82 32 1577.85 1797.56 89 1427.99 1734.82 33 1471.17 1797.56 90 1313.94 1734.82 34 1364.74 1797.56 91 1196.85 1734.82 35 1258.06 1797.56 92 1083.06 1734.82 36 1151.64 1797.56 93 965.96 1734.82 37 1044.96 1797.56 94 851.92 1734.82 38 938.53 1797.56 95 735.08 1734.82 39 831.85 1797.56 96 621.03 1734.82 40 725.42 1797.56 97 503.94 1734.82 41 618.74 1797.56 98 389.89 1734.82 42 512.32 1797.56 99 273.05 1734.82 43 405.64 1797.56 100 159.00 1734.82 44 299.21 1797.56 101 41.91 1734.82 45 192.53 1797.56 102 72.14 1734.82 46 86.11 1797.56 103 188.98 1734.82 47 20.57 1797.56 104 303.02 1734.82 48 127.00 1797.56 105 420.12 1734.82 49 233.45 1797.56 106 534.16 1734.82 50 340.11 1797.56 107 651.00 1734.82 51 446.53 1797.56 108 765.05 1734.82 52 553.21 1797.56 109 882.14 1734.82 53 659.64 1797.56 110 995.93 1734.82 54 766.83 1797.56 111 1113.03 1734.82 55 873.25 1797.56 112 1241.55 1781.81 56 979.68 1797.56 113 1347.98 1781.81 57 1100.07 1797.56 114 1454.66 1781.81 HTG2190 rev. 1.20 5 july 5, 2002 pad descriptions pad no. pad name i/o mask option description 37~1 114~112 seg0~seg39 o lcd segment signal output 53~38 com0~com15 o lcd common signal output 54~57 vout11, vout22 vout33, vout44 o lcd driving power generated 62, 61, 60, 58 cap1, cap2, cap3, cap4 lcd system voltage booster condenser connecting termi - nal. 59, 63 66, 67 trim1~trim4 test pin only 64 vss negative power supply, ground 68 65 osci osco i o crystal or rc osci and osco are connected to an rc network or a crys - tal (by mask option) for the internal system clock. in the case of rc operation,osci is connected to the rc network of the internal system clock. 69 vdd positive power supply 70 int /sin i int or serial data input selectable as external interrupt schmitt trigger input or serial data input by mask option. external interrupt schmitt trigger input with pull-high resistor. edge triggered activated on int or serial data input a high to low transition. serial data input with pull-high resistor. int shares pad with sin. 71 res i schmitt trigger reset input. active low without pull-high re- sistor. 72 pwm2/aud o pwm2 cmos output or aud output selectable as negative pwm cmos output or audio output by mask option. pwm2 share pad with aud. 73 pb0/pwm1 i/o or o i/o or pwm1 cmos output selectable as bidirectional input/output or positive pwm cmos output by mask option. on bidirectional input/output mode, software instructions determine whether each pad is a cmos output or schmitt trigger input with pull-high resis- tor. pb0 shares pad with pwm1. 74 pb7/tmr0 i/o or i i/o or tmr0 input selectable as bidirectional input/output or tmr0 input by mask option. on bidirectional input/output mode, software instructions determine whether it is a cmos output or schmitt trigger input with pull-high resistor. on tmr0 input mode, it uses timer/event counter 0. software can be optioned with or without pull-high resistor. pb7 shares pad with tmr0. 75 pb6/tmr1/rtf i/o or i i/o or tmr1 input or rtf input selectable as bidirectional input/output or tmr1 input or rtf input by mask option. on bidirectional input/output mode, software instructions determine whether it is a cmos output or schmitt trigger input with pull-high resistor. on tmr1 and rtf input mode, it uses timer/event coun - ter 1. software can be optioned with or without pull-high re - sister and be option the rtf function disable or enable. pb6 and tmr1 share pad with rtf. HTG2190 rev. 1.20 6 july 5, 2002 pad no. pad name i/o mask option description 76 pb5/sclk i/o i/o or sclk signal selectable as bidirectional input/output or serial interface clock signal by mask option. on bidirectional input/output mode, software instructions determine whe ther it is a cmos output or schmitt trigger input . serial i/o interface clock signal. at master mode: sclk should be set as serial clock output pin and after 8 clock output from sclk terminal, clock out - put is automatically suspended and sclk terminal is fixed at a high level. at slave mode: sclk should be set as serial clock input pin and after 8 clock input from sclk terminal, subsequent clock input are masked. pb5 shares pad with slck 77 pb4/sout i/o or o i/o or sout output selectable as bidirectional input/output or serial data output master by mask option. on bidirectional input/output mode, software in structions de termine whe ther it is a cmos output or schmitt trigger input . on serial output mode, sout pin is a cmos output. pb4 shares pad with sout. 78 79 pb3 pb2 i/o software instructions determine whether it is a cmos out - put or schmitt trigger input with pull-high resistor. when the pb6/tmr1/rtf pad is selected to be in rtf mode, the pb3, pb2 pull-high resistor is not present. 87~80 pa0~pa7 i/o wake-up or none wake-up bidirectional 8-bit input/output port. each bit can be config - ured as a wake-up input by mask option. software instruc - tions determine whe ther it is a cmos output or schmitt trigger input with pull-high resistor. 88 89 xin/pc7/seg63 xout/pc6/seg62 i or i/o or o crystal or i/o or segment output selectable as 32768hz crystal or bidirectional input/output or segment signal output by mask option. 32768hz crystal for timer3 and lcd clock source. xout and pc6 share with seg62 pad,xin and pc7 share with seg63 pad. 95~90 103~96 111~104 pc0~5/seg56~61 pd0~7/seg48~55 pe0~7/seg40~47 i/o or o i/o or segment output three bidirectional 8-bit input/output ports. software in- structions determine the cmos output or schmitt trigger in- put with pull-high resistor. pc, pd, pe can be individually optioned for segment output by mask option. pc0~pc7 share pads with seg56~seg63, pd0~pd7 share pads with seg48~seg55, and pe0~pe7 share pads with seg40~seg47. absolute maximum ratings supply voltage ......................................... 0.3v to 3.6v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature...............................0 cto70 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. HTG2190 rev. 1.20 7 july 5, 2002 d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 2.4 3.6 v i dd operating current (rc osc) 3v no load, f sys =4mhz 1 1.5 ma i stb1 standby current (rtc on, lcd on) 3v no load, halt 930 a i stb2 standby current (rtc on, lcd off) 3v no load, halt 3.5 15 a v il1 input low voltage for i/o ports 3v 0 0.9 v v ih1 input high voltage for i/o ports 3v 2.1 3v v il2 input low voltage (tmr0, tmr1, int )3v 0 0.7 v v ih2 input high voltage (tmr0, tmr1, int )3v 2.3 3v v il3 input low voltage (res )3v 1.5 v v ih3 input high voltage (res )3v 2.4 v i ol1 i/o ports sink current 3v v ol =0.3v 1.5 4 ma i oh1 i/o ports source current 3v v oh =2.7v 1 2 ma v lcd lcd voltage 3v 3.96 4.4 4.84 v i ol2 pwm1/pwm2 sink current 3v v ol =0.3v 12 16 ma i oh2 pwm1/pwm2 source current 3v v oh =2.7v 8 10 ma i ol3 audio sink current 3v v ol =0.3v 1.5 2 ma i oh3 audio source current 3v v oh =2.7v 1.5 2 ma i ol4 segment 0~39 output sink current 3v v ol =0.3v 80 130 a i oh4 segment 0~39 output source current 3v v oh =2.7v 50 90 a i ol5 segment 40~63 output sink current 3v v ol =0.3v 40 80 a i oh5 segment 40~63 output source current 3v v oh =2.7v 30 60 a r ph pull-high resistance of i/o ports, tmr0, tmr1 & int 3v 30 60 100 k a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock (rc osc) 3v 400 4000 khz f timer timer input frequency (tmr0,tmr1) 3v 0 4000 khz t wdtosc watchdog oscillator 3v 45 90 180 s t wdt watchdog time-out period (rc) 3v without wdt prescaler 12 23 45 ms t res external reset low pulse width 1 s t sst system start-up timer period power-up or wake-up from halt 1024 t sys t int interrupt pulse width 1 s note: t sys =1/f sys HTG2190 rev. 1.20 8 july 5, 2002 HTG2190 rev. 1.20 9 july 5, 2002 % & ' ( # # ! $ ) % ' * & % # # ! + $ % & ' ( # ! , $ ) % ' * & % # ! $ % & ' ( # # ! , $ ) % ' * & % # # ! , $ , , - . & % / # 0 1 ' 2 # ! # 1 3 0 - $ 4 3 2 4 3 2 4 3 2 4 3 2 # # # 5 & . 6 6 & 4 ' 2 # 4 3 2 # 1 5 3 & % 7 # # # # % 8 5 . & % 7 5 & " 5 & " 5 & # # " " # # # # # # * 9 9 % 7 4 & ' ( # : 4 & 4 # 1 3 # ) % ' * & 5 1 3 # 1 9 # ; * / < # 1 7 # 4 0 0 # 3 . & 7 * ' & 5 1 3 # 7 1 8 7 4 / # # : : 7 % . . 5 3 8 # 7 ' ( 5 & % ' & * 7 % # = 5 & . 7 1 8 7 4 / 1 * 3 & % 7 6 6 6 6 # 6 6 # execution flow functional description execution flow the system clock for the HTG2190 is derived from ei - ther a crystal or an rc oscillator. it is internally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute within one cycle. if an instruc - tion changes the program counter, two cycles are required to complete the instruction. program counter pc the 13-bit program counter (pc) controls the sequence in which the instructions stored in program rom are ex - ecuted. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call, initial re - set, internal interrupt, external interrupt or return from subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instruction. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is ob - tained. the lower byte of the program counter (pcl) is a read/write register (06h). moving data into the pcl per - mode program rom address *15 *14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 external or serial input interrupt 0000000000000100 timer/event counter 0 overflow 0000000000001000 timer/event counter 1 overflow 0000000000001100 timer 2 overflow 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 timer 3 overflow 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 skip pc+2 loading pcl *15 *14 *13 *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch bp.7 bp.6 bp.5 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program rom address note: *15~*0: program rom address s15~s0: stack register bits @7~@0: pcl bits bp.5~bp.7: bit 5~7 of bank pointer (04h) #12~#0: instruction code bits HTG2190 rev. 1.20 10 july 5, 2002 forms a short jump. the destination must be within 256 locations. when a control transfer takes place, an additional dummy cycle is required. program memory rom the program memory, which contains executable pro - gram instructions, data and table information, is com - posed of a 65536 x 16 bit format. however as the pc (program counter) is comprised of only 13 bits, the re - maining 3 rom address bits are managed by dividing the program memory into 8 banks, each bank having a range between 0000h and 1fffh. to move from the present rom bank to a different rom bank, the higher 3 bits of the rom address are set by the bp (bank pointer), while the remaining 13 bits of the pc are set in the usual way by executing the appropriate jump or call instruction. as the full 16 address bits are latched during the execution of a call or jump instruction, the correct value of the bp must first be setup before a jump or call is executed. when either a software or hardware inter - rupt is received, note that no matter which rom bank the program is in the program will always jump to the ap - propriate interrupt service address in bank 0. the origi - nal full 16 bit address will be stored on the stack and restored when the relevant ret/reti instruction is exe- cuted, automatically returning the program to the origi- nal rom bank. this eliminates the need for programmers to manage the bp when interrupts occur. certain locations in bank 0 of program memory are re- served for special usage: rom bank 0 (bp5~bp7=000b) the rom bank 0 ranges from 0000h to 1fffh. location 000h this area is reserved for the initialization program. af - ter a chip reset, the program always begins execution at location 000h. location 004h this area is reserved for the external interrupt or serial input interrupt service routine. if the int input pin is activated, and the interrupt is enabled and the stack is not full, the program will jump to location 004h and be - gins execution. location 008h/00ch this area is reserved for the timer/event counter 0/1 in - terrupt service program. if a timer interrupt results from a timer/event counter 0/1 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 008h/00ch and begins execution. location 010h/014h this area is reserved for the timer 2/3 interrupt service program. if a timer interrupt resulting from a timer 2/3 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 010h/014h and begins execution. location 018h this area is reserved for the pwm d/a buffer empty interrupt service program. after the system latch a d/a code at ram address 28h, the interrupt is enable, and the stack is not full, the program begins execution at location 018h. location 020h for best condition, this location is reserved as the be- ginning when writing a program. rom bank 1~7 (bp5~bp7=001b~111) the range of the rom starts from n000h to (n+1)fffh. (n=2,4,6,8,10,12,14) table location any location in the rom space can be used as look up table. the instructions tabrdc [m] (use for any bank) and tabrdl [m] (only used for last page of pro - gram rom) transfers the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the table is well-defined, the 6 6 6 % > 5 ' % # 5 3 5 & 5 4 0 5 ? 4 & 5 1 3 # < 7 1 8 7 4 / ) & % 7 3 4 0 # 1 7 # . % 7 5 4 0 # 5 3 < * & # 5 3 & % 7 7 * < & # . * = 7 1 * & 5 3 % 5 / % 7 % > % 3 & # ' 1 * 3 & % 7 # # 5 3 & % 7 7 * < & # . * = 7 1 * & 5 3 % 7 1 8 7 4 / # = 5 & . 6 5 / % 7 % > % 3 & # ' 1 * 3 & % 7 # # 5 3 & % 7 7 * < & # . * = 7 1 * & 5 3 % 6 5 / % 7 # 5 3 & % 7 7 * < & # . * = 7 1 * & 5 3 % 5 / % 7 # 5 3 & % 7 7 * < & # . * = 7 1 * & 5 3 % 6 6 # = * 9 9 % 7 # % / < & - # 5 3 & % 7 7 * < & 6 program memory instruction table location *15 *14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] #7 #6 #5 #4 #3 #2 #1 #0 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 11111111@7@6@5@4@3@2@1@0 table location note: @7~@0: tblp register bit7~bit0 *15~*0: program rom table address bit15~bit0 #7~#0: tbhp register bit7~bit0 HTG2190 rev. 1.20 11 july 5, 2002 higher-order byte of the table word are transferred to the tblh. the table higher-order byte register (tblh) is read only. the table pointer (tbhp, tblp) is a read/write register (1fh, 07h), used to indicate the table location. before accessing the table, the lo - cation must be placed in tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruction, the contents of the tblh in the main routine are likely to be changed by the table read in - struction used in the isr. if this happens errors can occur. in other words, using the table read instruction in the main routine and the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt(s) should be disabled prior to the table read instruction. it should not be enabled until the tblh has been backed up. all table related instructions need two cycles to complete the operation. these ar - eas may function as normal program memory de - pending upon requirements. stack register stack this is a special part of memory which is used to save the contents of the program counter (pc) only. the stack is organized into 8 levels and is neither part of the data nor program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledgment, the con- tents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, sig- naled by a return instruction (ret or reti), the program counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowl - edge will be inhibited. when the stack pointer is decre - mented (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow allowing the pro - grammer to use the structure more easily. in a similar case, if the stack is full and a call is subse - quently executed, stack overflow occurs and the first en - try will be lost (only the most recent eight return address are stored). data memory ram bank 0 (bp4~bp0=00000) the bank 0 data memory includes special purpose and general purpose memory. the special purpose memory is addressed from 00h to 3fh. all data mem - ory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. except for some dedicated bits, each bit in the data memory can be set and reset by the set [m].i and clr [m].i in - structions, respectively. they are also indirectly ac - cessible through the memory pointer registers (mp0;01h, mp1;03h). bank 1~11 (bp4~bp0=0001b~1011b) the range of ram starting from 40h to ffh are for general purpose. only mp1 can deal with the memory of this range. 6 @ 1 / / 1 3 # 4 : # : : 7 % . . # 1 & 4 & 1 7 # 4 & 4 # 1 a % 7 + 1 7 : % 7 # - & % # % 8 5 . & % 7 # 4 & 4 # 6 5 8 ( % 7 + 1 7 : % 7 # - & % # % 8 5 . & % 7 1 0 * / % # 1 3 & 7 1 0 # % 8 5 . & % 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 # # 4 & 4 # % 8 5 . & % 7 # # 1 3 & 7 1 0 # % 8 5 . & % 7 # # 4 & 4 # % 8 5 . & % 7 # # 1 3 & 7 1 0 # % 8 5 . & % 7 # # 4 & 4 # % 8 5 . & % 7 # # 1 3 & 7 1 0 # % 8 5 . & % 7 # # 4 & 4 # % 8 5 . & % 7 # # 1 3 & 7 1 0 # # 4 & 4 # % 8 5 . & % 7 # # 1 3 & 7 1 0 # % 8 5 . & % 7 3 : 5 7 % ' & # : : 7 % . . 5 3 8 # % 8 5 . & % 7 # % / 1 7 - # 1 5 3 & % 7 # 3 : 5 7 % ' & # : : 7 % . . 5 3 8 # % 8 5 . & % 7 # % / 1 7 - # 1 5 3 & % 7 # 4 3 2 # 1 5 3 & % 7 ' ' * / * 0 4 & 1 7 7 1 8 7 4 / # 1 * 3 & % 7 # 1 a % 7 + = - & % # % 8 5 . & % 7 4 = 0 % # 1 5 3 & % 7 # 1 a % 7 + 1 7 : % 7 # - & % # % 8 5 . & % 7 4 = 0 % # 6 5 8 ( % 7 + 1 7 : % 7 # - & % # % 8 5 . & % 7 4 & ' ( : 1 8 # 5 / % 7 # < & 5 1 3 # % & & 5 3 8 # % 8 5 . & % 7 & 4 & * . # % 8 5 . & % 7 3 & % 7 7 * < & # 1 3 & 7 1 0 # % 8 5 . & % 7 # 5 / % 7 # 1 * 3 & % 7 # # 6 5 8 ( % 7 + 1 7 : % 7 # - & % # % 8 5 . & % 7 5 / % 7 # 1 * 3 & % 7 # # 1 a % 7 + 1 7 : % 7 # - & % # % 8 5 . & % 7 5 / % 7 # 1 * 3 & % 7 # # 1 3 & 7 1 0 # % 8 5 . & % 7 5 / % 7 > % 3 & # 1 * 3 & % 7 # # 6 5 8 ( % 7 + 1 7 : % 7 # - & % # % 8 5 . & % 7 5 / % 7 > % 3 & # 1 * 3 & % 7 # # 1 a + 1 7 : % 7 # - & % # % 8 5 . & % 7 5 / % 7 > % 3 & # 1 * 3 & % 7 # # 1 3 & 7 1 0 # % 8 5 . & % 7 < % ' 5 4 0 # * 7 < 1 . % 4 & 4 # % / 1 7 - 3 & % 7 7 * < & # 1 3 & 7 1 0 # % 8 5 . & % 7 # 4 = 0 % # 1 5 3 & % 7 # 6 5 8 ( % 7 + 1 7 : % 7 # - & % # % 8 5 . & % 7 5 / % 7 # # % 8 5 . & % 7 5 / % 7 # # 1 3 & 7 1 0 # % 8 5 . & % 7 5 / % 7 # # % 8 5 . & % 7 5 / % 7 # # 1 3 & 7 1 0 # % 8 5 . & % 7 @ & 4 0 # 4 . & # . ' 5 0 0 4 & 1 7 # * < # 1 3 & 7 1 0 # 1 3 & 7 1 0 # 4 & 4 % 7 5 4 0 # 1 3 & 7 1 0 % 7 5 4 0 # 4 & 4 1 0 1 7 # # 4 0 % & & % . 1 0 1 7 # # 4 0 % & & % . 1 0 1 7 # # 4 0 % & & % . 1 0 1 7 # # 4 0 % & & % . 4 3 2 # # 4 & 4 # % / 1 7 - ! # - & % $ % 3 % 7 4 0 # * 7 < 1 . % 4 3 2 # # 4 & 4 # % / 1 7 - ! # - & % $ 4 3 2 # # 4 & 4 # % / 1 7 - ! # - & % $ % 3 % 7 4 0 # * 7 < 1 . % 4 3 2 # # 4 & 4 # % / 1 7 - ! # - & % $ % 3 % 7 4 0 # * 7 < 1 . % 4 3 2 # # 4 & 4 # % / 1 7 - ! # - & % $ 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 b # 3 * . % : ram mapping HTG2190 rev. 1.20 12 july 5, 2002 bank 14/15 (bp4~bp0=01110b~01111b) the range of ram starts from 80h to ffh. every bit stands for one dot on the lcd. if the bit is 1 , the light of the dot on the lcd will be turned on. if the bit is 0 , then it will be turned off. only mp1 can deal with the memory of this range. the contrast form of ram location, common, and segment is as follows. lcd driver output the maximum output number of the HTG2190 lcd driver is 16 64. the common output signal can be se - lected as 16 com or 8 com by mask option. the lcd driver bias type is c type, external capacitor is re - quired and the bias voltage is 1/4 bias. some of the seg - ment outputs share pins with i/o pins, pe0~pe7 (seg40~47), pd0~pd7(seg48~55) and pc0~pc7 (seg56~63). whether segment output or i/o pin can be decided by mask option. lcd driver output can be enabled or disabled by setting col3 (bit 6 of col3; 2eh) without the influence of the related memory condition. on the color lcd mode: every two bits stands for one dot on the ecb. if the both bits is not 0, the light of the dot on the ecb will be turned on. if the both bits is 0, then it will be selected to color 0. only mp1 can be deal with the memory of this range. the contrast form of ram location, common, and segment is as follows. address d7 d6 d5 d4 d3 d2 d1 d0 80h seg0~com3 seg0~com2 seg0~com1 seg0~com0 81h seg0~com7 seg0~com6 seg0~com5 seg0~com4 82h seg1~com3 seg1~com2 seg1~com1 seg1~com0 83h seg1~com7 seg1~com6 seg1~com5 seg1~com4 84h seg2~com3 seg2~com2 seg2~com1 seg2~com0 85h seg2~com7 seg2~com6 seg2~com5 seg2~com4 fah seg61~com3 seg61~com2 seg61~com1 seg61~com0 fbh seg61~com7 seg61~com6 seg61~com5 seg61~com4 fch seg62~com3 seg62~com2 seg62~com1 seg62~com0 fdh seg62~com7 seg62~com6 seg62~com5 seg62~com4 feh seg63~com3 seg63~com2 seg63~com1 seg63~com0 ffh seg63~com7 seg63~com6 seg63~com5 seg63~com4 lcd ram mapping bank14 address d7 d6 d5 d4 d3 d2 d1 d0 80h seg0~com11 seg0~com10 seg0~com9 seg0~com8 81h seg0~com15 seg0~com14 seg0~com13 seg0~com12 82h seg1~com11 seg1~com10 seg1~com9 seg1~com8 83h seg1~com15 seg1~com14 seg1~com13 seg1~com12 84h seg2~com11 seg2~com10 seg2~com9 seg2~com8 85h seg2~com15 seg2~com14 seg2~com13 seg2~com12 fah seg61~com11 seg61~com10 seg61~com9 seg61~com8 fbh seg61~com15 seg61~com14 seg61~com13 seg61~com12 fch seg62~com11 seg62~com10 seg62~com9 seg62~com8 fdh seg62~com15 seg62~com14 seg62~com13 seg62~com12 feh seg63~com11 seg63~com10 seg63~com9 seg63~com8 ffh seg63~com15 seg63~com14 seg63~com13 seg63~com12 lcd ram mapping bank15 HTG2190 rev. 1.20 13 july 5, 2002 register address bit no. label description col0 2bh 0~4 p0~p4 color0 palette 5~7 unused bit read only col1 2ch 0~4 p0~p4 color1 palette 5~7 unused bit read only col2 2dh 0~4 p0~p4 color2 palette 5~7 unused bit read only how to select the color: dn+1 dn color 0 00 color 1 01 color 2 10 color 3 11 segment common lcdc register register bit no. label function col3 0~4 p0~p4 color3 palette 5 unused bit, read as 0 6 lcd controls the lcd output (0=disable, 1=enable) (default=1) 7rc lcd clock source select (default=0) 1=32768hz crystal 0=system clock (note*) col3 register note: * when the mask option is selected to 32k x tal disable, user should be set 0 to col3.7. but the 32k x tal can t be disabled in the ht-ide2000 tools, so user should take care of this difference. an example of an ecb driving waveform is shown below: 8 com, 1/4 bias lcd clock source=16384hz # # # # # # a @ a @ + + 6 ? + 1 & % b # @ # % 4 0 # 4 ' & 5 > % # . % 8 / % 3 & # . 5 8 3 4 0 # a 5 : & ( # @ c # # # # # # # # # # # # # # # # # # # ! 4 : d * . & 4 = 0 % # a 5 : & ( # = - # # : : 7 % . . # # # # # # # # # # 6 " 6 " 6 # = 5 & e = 5 & $ # # # # # # # # # # b # 4 ) f # 4 ' & 5 > % # . % 8 / % 3 & # . 5 8 3 4 0 # a 5 : & ( e HTG2190 rev. 1.20 14 july 5, 2002 16com, 1/4bias lcd clock source=32768hz on the bw lcd mode: bank14 has a general purpose data ram and for bank15, every 1 bit stands for one dot on the lcd. if the bits is not 0, the light of the dot on the lcd will be turned on. if the bits is 0, then it will be turned off. only mp1 can deal with the memory of this range. the contrast form of ram location, common and segment is as follows: address 80h 81h 82h 83h 84h 85h --------------------91h 92h ---- ---- ---- bfh com0 bit0 com1 bit1 com2 bit2 com3 bit3 com4 bit4 com5 bit5 com6 bit6 com7 bit7 address c0h c1h c2h c3h c4h c5h ------------------------- ---- ---- ---- feh ffh com8 bit0 com9 bit1 com10 bit2 com11 bit3 com12 bit4 com13 bit5 com14 bit6 com15 bit7 seg0 seg1 seg2 seg3 seg4 seg5 -------------seg17 seg18 ---- ---- ---- seg63 lcd display memory: (bank15) # # # # # # a @ a @ + + 6 ? + 1 & % b # @ # % 4 0 # 4 ' & 5 > % # . % 8 / % 3 & # . 5 8 3 4 0 # a 5 : & ( # @ c # # # # # # # # # # # # # # # # # # # ! 4 : d * . & 4 = 0 % # a 5 : & ( # = - # # : : 7 % . . # # # # # # # # # # 6 " 6 " 6 # = 5 & e = 5 & $ # # # # # # # # # # b # 4 ) f # 4 ' & 5 > % # . % 8 / % 3 & # . 5 8 3 4 0 # a 5 : & ( e HTG2190 rev. 1.20 15 july 5, 2002 an example of an lcd driving waveform is shown below. 8 com, 1/4 bias 16 com, 1/4 bias 6 ? # # # # # # # # # 6 ? 6 ? # # # # # # # # # 6 ? HTG2190 rev. 1.20 16 july 5, 2002 ssl3 ssl2 ssl1 ssl0 description x000 the pad of common 0 is connected to common 0 signal and the pad of common 1 is connected to common 1 signal and so on. x001 the pad of common 0 is connected to common 1 signal and the pad of common 1 is connected to common 2 signal and so on. x010 the pad of common 0 is connected to common 2 signal and the pad of common 1 is connected to common 3 signal and so on. x011 the pad of common 0 is connected to common 3 signal and the pad of common 1 is connected to common 4 signal and so on. x100 the pad of common 0 is connected to common 4 signal and the pad of common 1 is connected to common 5 signal and so on. x101 the pad of common 0 is connected to common 5 signal and the pad of common 1 is connected to common 6 signal and so on. x110 the pad of common 0 is connected to common 6 signal and the pad of common 1 is connected to common 7 signal and so on. x111 the pad of common 0 is connected to common 7 signal and the pad of common 1 is connected to common 0 signal and so on. comr register indirect addressing register locations 00h and 02h are indirect addressing regis - ters that are not physically implemented. any read/write operation of [00h] and [02h] access data memory pointed to by mp0 (01h) and mp1 (03h) respectively. reading location 00h or 02h indirectly returns the result 00h, while writing to it indirectly results in no operation. the data movement function between two indirect ad- dressing registers is not supported. the memory pointer registers mp0 and mp1, are 8-bit registers used to ac- cess the data memory by combining corresponding indi- rect addressing registers, bank1~bank11, bank14 and bank15 can use mp1 only. accumulator the accumulator closely relates to alu operations. it is also mapped to location 05h of the data memory and is the one which can operate with immediate data. the data movement between two data memory must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic operation. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but can also change the status register. status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pd) and watchdog time-out flag (to). it also records the status information and controls the oper- ation sequence. with the exception of the to and pd flags, bits in the status register can be altered by instructions like any other register. any data written into the status register will not change the to or pd flags. in addition, opera- tions related to the status register may give different re- sults from those intended. the to and pd flags can only be changed by a system power up, watchdog timer overflow, executing the halt instruction and clearing the watchdog timer. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or exe - cuting the subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status register are important and the subroutine can corrupt the status register, the programmer must take precautions to save it properly. interrupt the HTG2190 provides external and a pwm d/a inter - rupt and internal timer/event counter interrupts. the in - terrupt control register (intc;0bh, intch;1eh) contains the interrupt control bits to set the enable/disable and the interrupt request flags. HTG2190 rev. 1.20 17 july 5, 2002 once an interrupt subroutine is serviced, all other inter - rupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may happen during this interval but only the interrupt request flag is recorded. if a certain in - terrupt needs servicing within the service routine, the emi bit and the corresponding intc bit may be set to allow in- terrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is en- abled, until the sp is decremented. if immediate service is desired, the stack must be prevented from becoming full. all these kinds of interrupt have the wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter and a15~a13 bits onto the stack and then branching to subroutines at specified lo - cation(s) in the program memory. only the program counter are pushed and a15~a13 bits onto the stack. if the contents of the register and status register (status) are altered by the interrupt service program which corrupt the desired control sequence, the con - tents must be saved first. external interrupt is triggered by a high to low transition of int which sets the related interrupt request flag (eif; bit 4 of intc0). when the interrupt is enabled, and the stack is not full and the external interrupt is active, a sub - routine call to location 04h will occur. the interrupt re - quest flag (eif) and emi bits will be cleared to disable other interrupts. the internal timer/event counter 0 interrupt is initial - ized by setting the timer/event counter 0 interrupt re - quest flag (t0f; bit 5 of intc0), caused by a timer/event counter 0 overflow. when the interrupt is enabled, and the stack is not full and the t0f bit is set, a subroutine call to location 08h will occur. the related in - terrupt request flag (t0f) will be reset and the bit cleared to disable further interrupts. the timer/event counter 1 and timer 2/3 interrupt is op - erated in the same manner as timer/event counter 0. the related interrupt control bits et1i and t1f of timer/event counter 1 are bit 3 and bit 6 of intc0 re - spectively. while et2i/et3i and t2f/t3f are the re - lated control bits and the related request flags of tmr2/tmr3, which locate at bit0/bit1 and bit4/bit5 of the intc1 respectively. during the execution of an interrupt subroutine, other inter- rupt acknowledgments are held until the reti instruction is executed or the emi bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). to return from the interrupt subroutine, the ret or reti instruction may be invoked. reti will set the emi bit to enable an interrupt service, but ret will not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt 1 04h timer/event counter 0 overflow 2 08h timer/event counter 1 overflow 3 0ch timer 2 overflow 4 10h timer 3 overflow 5 14h pwm d/a interrupt 6 18h the timer/event counter 0/1 and timer 2/3 interrupt re - quest flag (t0f/t1f/t2f/t3f), external interrupt request flag (eif), pwm d/a interrupt request flag (pwmf) enable timer/ event counter 0/1/2/3 bit (et0i/et1i/et2i/ et3i), enable pwm d/a interrupt bit (pwmi), enable external in - terrupt bit (eei) and enable master interrupt bit (emi) form labels bits function c0 c is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. also it is affected by a rotate through carry instruction. ac 1 ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z 2 z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. ov 3 ov is set if the operation results in a carry into the highest-order bit but not a carry out of the high - est-order bit, or vice versa; otherwise ov is cleared. pd 4 pd is cleared when either a system power-up or executing the clr wdt instruction. pd is set by executing the halt instruction. to 5 to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6,7 unused bit, read as 0 status register HTG2190 rev. 1.20 18 july 5, 2002 the interrupt control register (intc0/intc1) located at 0bh/1eh in the data memory. emi, eei, et0i, et1i, et2i, et3i, pwmi, are used to control the enabling/disabling of interrupts. these bits prevent the requested interrupt be- ing serviced. once the interrupt request flags (t0f, t1f, t2f, t3f, eif, pwmf) are set, they will remain in the intc0/intc1 register until the interrupts are serviced or cleared by a software instruction. it is recommended that application programs do not use call subroutines within an interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt enable is not well controlled, once a call subroutine if used in the interrupt sub - routine will corrupt the original control sequence. oscillator configuration there are two oscillator circuit in the HTG2190. the rc oscillator signal provides the internal system clock. the halt mode stops the system oscillator and ignores any external signal to conserve power. only the rc oscillator is designed to drive the internal system clock. the rtc oscillator provides the timer3 and lcd driver clock source. the rc oscillator needs an external resistor connected between osci and v ss . the resistance value must range from 50k ~400k however, the frequency of the oscillator may vary with v dd , temperature and the chip itself due to process vari - ations. it is, therefore, not suitable for timing sensitive operations where accurate oscillator frequency is de - sired. the rtc oscillator is used to provide clock source for lcd driver and timer3. it can be enabled or disabled by mask option. there is another oscillator circuit designed for the real time clock. in this case, only the 32768hz crystal oscilla - tor can be applied. the crystal should be connected be - tween and xout, and two external capacitors along with one external resistor are required for the oscillator circuit in order to get a stable frequency. register bit no. label function intc0 0 emi master (global) interrupt (1=enable; 0=disable) 1 eei external interrupt (1=enable; 0=disable) 2 et0i timer/event counter 0 interrupt (1=enable; 0=disable) 3 et1i timer/event counter 1 interrupt (1=enable; 0=disable) 4 eif external interrupt request flag (1=active; 0=inactive) 5 t0f internal timer/event counter 0 request flag. (1=active; 0=inactive) 6 t1f internal timer/event counter 1 request flag. (1=active; 0=inactive) 7 unused bit, read as 0 intc0 register register bit no. label function intc1 0 et2i controls the timer 2 interrupt. (1=enable; 0=disable) 1 et3i controls the timer 3 interrupt. (1=enable; 0=disable) 2 pwmi pwm d/a interrupt (1=enable; 0=disable) 3 should be set 0 always. 4 t2f internal timer 2 request flag. (1=active; 0=inactive) 5 t3f internal timer 3 request flag. (1=active; 0=inactive) 6 pwmf pwm d/a flag (1=enable; 0=disable) 7 should be set 0 always. intc1 register # . ' 5 0 0 4 & 1 7 6 ? # . ' 5 0 0 4 & 1 7 system and rtc oscillator HTG2190 rev. 1.20 19 july 5, 2002 the wdt oscillator is a free running on-chip rc oscilla - tor, requiring no external components. even if the sys - tem enters the power down mode, and the system clock is stopped, the wdt oscillator still runs with a period of approximately 78 s. the wdt oscillator can be dis - abled by mask option to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator). this timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. the watchdog timer can be disabled by a mask option. if the watchdog timer is disabled, all the executions re - lated to the wdt result in no operation. once the internal wdt oscillator (rc oscillator with a nominal period of 78 s) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of ap - proximately 20 ms. this time-out period may vary with temperature, vdd and process variations. by invoking the wdt prescaler, longer time-out periods can be real - ized. writing data to ws2, ws1, ws0 (bit 2,1,0 of the wdts) can give different time-out periods. if ws2, ws1, ws0 all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds. ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 wdts register if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom - mended, since the halt will stop the system clock. the wdt overflow under normal operation will initialize a chip reset and set the status bit to . whereas in the halt mode, the overflow will initialize a warm re - set only the pc and sp are reset to zero. to clear the contents of the wdt (including the wdt prescaler ), three methods are adopted; external reset (a low level to res ), software instructions, or a halt instruction. the software instruction is clr wdt and execution of the clr wdt instruction will clear the wdt. power down operation halt the halt mode is initialized by a halt instruction and results in the following. the system oscillator will turn off but the wdt oscilla - tor keeps running (if the wdt oscillator is selected). the contents of the on chip ram and registers remain unchanged. wdt and wdt prescaler will be cleared and recount again. all i/o ports maintain their original status. the pd flag is set and the to flag is cleared. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig - nal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow per - forms a warm reset . by examining the to and pd flags, the reason for the chip reset can be determined. the pd flag is cleared when the system powers-up or executing the clr wdt instruction and is set when the halt in - struction is executed. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the pc and sp. the others maintain their original status. the port a wake-up and interrupt methods can be con- sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by a mask option. awakening from an i/o port stimulus, the program will resume execution of the next instruction. if awakening from an interrupt, two se- quences may happen. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the pro- gram will resume execution at the next instruction. if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. once a wake-up event occurs, it takes 1024 t sys (sys - tem clock period) to resume normal operation. in other words, a dummy cycle period will be inserted after a wake-up. if the wake-up results from an interrupt ac - knowledge, the actual interrupt subroutine will be de - layed by one more cycle. if the wake-up results in next instruction execution, this will be executed immediately after a dummy period is finished. if an interrupt request + = 5 & # 1 * 3 & % 7 # 7 % . ' 4 0 % 7 + = 5 & # 1 * 3 & % 7 + & 1 + # # 5 / % + 1 * & e watchdog timer HTG2190 rev. 1.20 20 july 5, 2002 flag is set to 1 before entering the halt mode, the wake-up function of the related interrupt will be disabled. to minimize power consumption, all i/o pins should be carefully managed before entering the halt status. reset there are 3 ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a warm re - set that resets only the pc and sp, leaving the other circuits in their original state. some registers remain un - changed during any other reset conditions. most regis - ters are reset to their initial condition when the reset conditions are met. by examining the pd flag and to flag, the program can distinguish between different chip resets . to pd reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchange to guarantee that the system oscillator has started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses after a system power up or when awakening from a halt state. when a system power up occurs, the sst delay is added during the reset period. but when the reset co - mes from the res pin, the sst delay is disabled. any wake-up from halt will enable the sst delay. the functional unit chip reset status is shown in the ta- ble. program counter 000h interrupt disable prescaler clear wdt clear. after master reset, wdt begins counting timer/event counter (0/1/2/3) off lcd display enable pull-high of tmr0/tmr1 with pull-high resistor input/output ports input mode sp points to the top of the stack reset circuit 6 5 / % + 1 * & % . % & 1 0 : % . % & 4 7 / # % . % & 1 a % 7 + 1 3 # % & % ' & 5 3 8 + . & 4 8 % 5 < < 0 % # 1 * 3 & % 7 reset configuration & # 5 / % + 1 * & ( 5 < # # % . % & reset timing chart the state of the registers is summarized in the following table: register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* tmr1h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- tmr0h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu HTG2190 rev. 1.20 21 july 5, 2002 register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* tmr0l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- tmr2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr2c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu tmr3 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr3c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu intch 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tbhp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 0000h 0000h 0000h 0000h 0000h mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu bp 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu intcl -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pwmc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pwm xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu serc -111 1111 -111 1111 -111 1111 -111 1111 -111 1111 serdata xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu col0 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 col1 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 col2 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 col3 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 dal 0000 ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- dah 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 volc 0000 ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu x tal 0000 1100 0000 1100 0000 1100 0000 1100 0000 1100 note: * stands for warm reset u stands for unchange x stands for unknown stands for unknown HTG2190 rev. 1.20 22 july 5, 2002 timer/event counter 0/1 two timer/event counters are implemented in the HTG2190. the timer/event counter 0 and 1 contain 16-bit programmable count-up counters whose clock may come from an external source or the system clock divided by 4. it should be noted that, if the timer/event counter 0 is selected, the tmr0 pin should be enabled by mask option. the pull-high resistor can be disabled or enabled by software instruction. using the internal instruction clock, there is only one ref - erence time-base. the external clock input allows the user to count external events, measure time intervals or pulse width, or to generate an accurate time base. there are three registers related to timer/event coun - ter 0; tmr0h (0ch), tmr0l (0dh), tmr0c (0eh). writing to tmr0l only writes the data into a low byte buffer. writing to tmr0h will write the data and the con - tents of the low byte buffer into the timer/event counter 0 preload register (16-bit) simultaneously. the timer/event counter 0 preload register is changed only by a write to tmr0h operation. writing to tmr0l will keep the timer/event counter 0 preload register un - changed. reading tmr0h will also latch the tmr0l into the low byte buffer to avoid false timing problems. reading the tmr0l only returns the value from the low byte buffer which may be a previously loaded value. in other words, the low byte of timer/event counter 0 cannot be read di - ! & - @ ( ) - & , # & - ( 6 & & ( - & ( 6 & ( " c & * ! * $ $ & * - 6 $ - c & timer/event counter 0/1 label bits function 0~2 unused bit, read as 0 te 3 defines the tmr0/tmr1 active edge of timer/event counter (0=active on low to high; 1=active on high to low) ton 4 enable/disable timer counting (0=disabled; 1=enabled) 5 unused bit, read as 0 tm1, tm0 7, 6 define the operating mode (tm1, tm0) 01=event count mode (external clock) 10=timer mode (internal clock) 11=unused 00=unused tmr0c/tmr1c register label bits function fast 0 0=speed-up 32k x'tal (default) 1=non-speed-up 32k x'tal rtf 1 select the r-to-f function 0=disable r-to-f (default), 1=enable r-to-f rtmr0 2 select the tmr0 pull-high resistor (1=with pull-high; 0=without pull-high) rtmr1 3 select the tmr1 pull-high resistor (1=with pull-high; 0=without pull-high) vdet 4 supply voltage detection circuit (1=enable vdet, 0=disable vdet) 5~7 unused bit, read as 0 x'talc register HTG2190 rev. 1.20 23 july 5, 2002 rectly. it must read the tmr0h first to ensure that the low byte contents of timer/event counter 0 are latched into the buffer. there are three registers related to the timer/event counter 1; tmr1h (0fh), tmr1l (10h), tmr1c (11h). the timer/event counter 1 oper ates in the same manner as timer/event counter 0. the tmr0c is the timer/event counter 0 control regis - ter, which defines the timer/event counter 0 options. the timer/event counter 1 has the same options as the timer/event counter 0 and is defined by tmr1c. the timer/event counter control registers define the op - erating mode, counting enable or disable and active edge. the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which implies that the clock source comes from an ex - ternal (tmr0/tmr1) pin. the timer mode functions as a normal timer with the clock source coming from the in - struction clock. the pulse width measurement mode can be used to count the high or low level duration of an external signal (tmr0/tmr1). the counting method is based on the instruction clock. in the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to ffffh. once overflow occurs, the counter is reloaded from the timer/event counter preload register and generates a corresponding interrupt request flag (t0f/t1f; bit 5/6 of intc) at the same time. to enable the counting operation, the timer on bit (ton; bit 4 of tmr0c/tmr1c) should be set to 1. in the pulse width measurement mode, ton will be cleared automatically after the measurement cycle is complete. but in the other two modes ton can only be reset by in - struction. the overflow of the timer/event counter is one of the wake-up sources. no matter what the operation mode is, writin ga0to et0i/et1i can disable the corre - sponding interrupt service. in the case of a timer/event counter off condition, writ - ing data to the timer/event counter preload register will also reload that data to the timer/event counter. but if the timer/event counter is turned on, data written to the timer/event counter will only be kept in the timer/event counter preload register. the timer/event counter will continue to operate until an overflow oc - curs. when the timer/event counter (reading tmr0h/ tmr1h) is read, the clock will be blocked to avoid er - rors. as this may result in a counting error, this must be taken into consideration by the programmer. low voltage detect function (lvd) the HTG2190 provides low voltage detect to monitor the supply voltage of devices. the user can use the x talc.4 to enable/disable (1/0) the lvd function and read the lvd detect status (0/1) from x talc.4 otherwise, the lvd function is disabled. if the x talc.4 is 1 , means low battery otherwise if still work (v d =(v22+150mv) 100mv, v d means voltage detect value). r to f function the HTG2190 provides an rtof (resistor to fre - quency) function for temperature measurement and so on. the application circuit is shown below. r1 is a fixed resistor about 10k for reference, while r2 is a thermistor whose resistance is variable according to the temperature. c is a capacitance about 2200pf for charge and discharge purposes. it should be noted that, if the r to f function is selected, the pull-high resistors of tmr1. the tmr1 pull-high resistor can be disabled by software instruction. the related frequency of r1 is measured by setting pb3 to be an output pin and pb2 to be an input pin. then set the pb3 to be a source current to charge the capacitance c. if the charged voltage ar - * . * 4 . r to f application circuit > & & & < b " g 4 = 8 9 & < b " g = r to f structure HTG2190 rev. 1.20 24 july 5, 2002 rives as v ih (input high voltage) of s1 gate, the nmos will be turned on for discharge. the same manner can be used for measuring the related frequency of r2, but the roles of pb2 and pb3 should be exchanged. during execution of r to f function, the tmr1 should be set as event counter to count the charge/discharge waveform. since the falling edge of the charge/dis - charge waveform is sharper than the rising edge, it is recommended that the active edge of the event counter on high to low be defined by setting te (bit 3 of tmr1c). for other detailed operation about timer/event counter 1, refer to a related section of the timer/event counter 0/1. an example of a software program written for the pur - pose of measuring related frequency of r2 is shown be - low. set pbc.3 ; set pb.3 to be input pin clr pbc.2 ; set pb.2 to be output pin set pb.2 ; output source current at pb.2 clr x talc.3 ; disable tmr1 pull-high resistor mov a, 48h ; set tmr1 to be event counter mov tmr1c, a ; and active edge on high to low clr tmr1l ; set tmr1l and tmr1h to be 00 clr tmr1h ; set tmr1c.4 ; turn on tmr1 set xt alc.1 ; turn on r to f function timer 2/3 timer 2 is an 8-bit counter, and its clock source come from the system clock divided by an 8-stage prescaler. there are two registers related to timer 2 ; tmr2 (21h) and tmr2c (22h). two physical registers are mapped to tmr2 location; writing to tmr2 makes the starting value be placed in the timer 2 preload register and reading the tmr2 obtains the contents of the timer 2 counter. the tmr2c is a control register, which defines the division ratio of the prescaler and counting enable or disable. writing data to b2, b1 and b0 (bit 2, 1, 0 of tmr2c) can generate various clock source. once the timer 2 starts counting, it will count from the current contents in the counter to ffh. once an over - flow occurs, the counter is reloaded from the preload register, and generates an interrupt request flag (t2f; bit 4 of the intch). to enable the counting operation, the timer on bit (ton ; bit 4 of tmr2c) should be set to 1 . for proper operation, bit 6 of tmr2c should be set to 1 , and bit3, bit7 should be set to 0 . timer 2 can also be used as a buzzer output by setting pb.0 and aud to be pwm1 and pwm2 output respec - tively by mask option. when the pwm1/pwm2 is se - lected, setting 2fh.6/2fh.7 to 1 will select pfd/pfdb output and setting 2fh.6/2fh.7 to 0 will select pwm1/pwm2 output. when the pfd/pfdb function is selected, setting 2fh.4/2fh.5 to 1 will enable pfd/pfdb output and setting 2fh.4/2fh.5 to 0 will disable pfd/pfdb output. pfd frequency= t2f/ [(256-tmr2) 2]. tmr2c t2f b2 b1 b0 0 0 0 sys clk/2 0 0 1 sys clk/4 0 1 0 sys clk/8 0 1 1 sys clk/16 1 0 0 sys clk/32 1 0 1 sys clk/64 1 1 0 sys clk/128 1 1 1 sys clk/256 tmr2c bit4 to enable/disable timer counting (0=dis - able;1=enable) tmr2c bit3, always write 0 tmr2c bit5, always write 0 tmr2c bit6, always write 1 tmr2c bit7, always write 0 : " charge/discharge waveform HTG2190 rev. 1.20 25 july 5, 2002 label bits function ssl3~0 3~0 lcd common used pfd 4 enable/disable pfd output (0=disable, 1=enable) pfdb 5 enable/disable pfdb output (0=disable, 1=enable) pwm1 6 select pfdb/pwm1 output (0=pwm1, 1=pfdb) pwm2 7 select pfd/pwm2 output (0=pwm2, 1=pfd) comr register tmr3c t3f b2 b1 b0 0 0 0 f1/2 0 0 1 f1/4 0 1 0 f1/8 0 1 1 f1/16 1 0 0 f1/32 1 0 1 f1/64 1 1 0 f1/128 1 1 1 f1/256 f1 can select 4 frequencies by mask option auto mask option f0 system clock near 512khz f sys /16 system clock near 1024khz f sys /32 system clock near 2048khz f sys /64 system clock near 4096khz f sys /128 time base frequency = t3f / (256 tmr3) tmr3c bit 4 to enable/disable timer counting (0=dis - able; 1=enable) tmr3c bit6, always write 1 tmr3c bit7, always write 0 tmr3c bit 3, always write 0 timer 3 has the same structure and operating manner with timer 2, except for clock source and pfd function. the timer 3 can be used as a time base to generate a regular internal interrupt. the clock source of timer 3 can come from rtc osc (x'tal 32khz) or system clock divided by an 8-stage prescaler. if the rtc mask option is enabled, a 32khz crystal is needed to connect across xin and xout pins. the 32khz signal is processed by an 8-stage prescaler to generate various counting clock for timer 3. there are two registers related to timer 3; tmr3 (24h) and tmr3c (25h). writing data to b2, b1, b0 (bit 2, 1, 0 of tmr3c) can generate various counting clock. ! & - @ 3 8 - & . - & & . & * - 6 $ - c . 9 : g ) & . $ . . 9 : g / , . . 9 : g 1 , . , . 9 : g + , timer 2 & 4 - 3 & & - " & 6 < . ) : ; = 4 . ' & b " . : g 1 3 & & - ! - @ 9 9 4 $ & 4 . 1 + 3 : ; 4 . @ & h h & $ & # & 3 & & * ( , & & & - 5 & # & 6 - & $ & # & 6 & & + ) g & & $ & # & + & & * ( , & & & - 5 & # & 6 - & $ & # & 6 & & 4 . g & & $ & # & 3 & & * & & & - 5 & # & 6 - & $ & # & 6 & & . g & & $ & # & + & & * & & & - 5 & # & 6 - & $ & # & 6 & & g timer 3 HTG2190 rev. 1.20 26 july 5, 2002 input/output ports there are 39 bidirectional input/output lines in the HTG2190, labeled from pa to pe, which are mapped to the data memory of [12h], [14h], [16h], [18h], [1ah], re - spectively. all these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h, 16h, 18h, 1ah). for output operation, all data is latched and remain unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pcc, pdc, pec) which controls the input/output configura - tion. with this control register, cmos output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e., on-the-fly) under software control. to function as an input, the corre - sponding latch of the control register must write 1 . the pull-high resistance will be exhibited automatically if the pull-high option is selected. the input source also de - pends on the control register. if the control register bit is 1 input will read the pad state. if the control register bit is 0 the contents of the latches will move to the internal bus. the latter is possible in read-modify-write instruc - tion. for output function, cmos is the only configura - tion. these control registers are mapped to locations 13h, 15h, 17h, 19h, 1bh. after a chip reset, these input/output lines stay at schmitt trigger input with pull-high resistor. each bit of these input/output latches can be set or cleared by the set [m].i or clr [m].i (m=12h, 14h, 16h, 18h, 1ah) in- struction. some instructions first input data and then follow the output operations. for example, the set [m].i, clr [m].i, cpl [m] and cpla [m] instructions read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has a wake-up capability. pc, pd and pe can be selected as segment output by mask option. if the segment output is selected, the related i/o register (pc, pd and pe) cannot be used as a general purpose register. reading the register will result to an unknown state. pwm interface the HTG2190 provides an 8 bit (bit7 is a sign bit) pwm d/a interface, which is good for speech synthesis. the user can record or synthesize the sound and digitize it into the program rom. these sound could be played back in sequence of the function as designed by the internal program rom. there are several algorithms that can be used in the HTG2190, they are pcm, law, dpcm, adpcm..... the pwm circuit provides two pad outputs: pwm2, pwm1 which can directly drive a piezo or a 32 speaker without adding any external element. refer to the appli - cation circuits. the pwm clock source comes from the system clock di - vided by a 3-bit prescaler. setting data to p0, p1 and p2 (bit 3, 4, 5 of 27h) can generate various clock sources. the clock source are used for pwm modulating clock and sampling clock. after setting the start bit (bit 0 of 27h) and the next falling edge coming from the prescaler, the div will generate a serial clock to pwm counter for modulation and pwmi for interrupt. the pwm counter latch data at the first f1 clock falling edge and the start counter at f1 rising edge. the pwm base frequency is 32khz. for every 32khz latch data once. the f2 clock is synchronous with the first f1 clock and it is also connected to the pwm output latch. in setting the start bit initial status, the pwm1 dac outputs a low level and change the output status to high while the 7-bit counter overflows. i ' i i ' i & * , & - & # & & - & , & ( & ( ! & , @ 8 & < & - ! = , @ - - 8 2 1 * 5 & * . 2 * 1 2 1 2 1 2 1 @ & @ & input/output ports HTG2190 rev. 1.20 27 july 5, 2002 bz/sp 6/7 bit f1 f2 (sampling rate) device 0 0 f0 f0/64 32 speaker 0 1 f0 f0/128 32 speaker 1 0 f0 f0/64 buzzer/8 speaker 1 1 f0 f0/128 buzzer/8 speaker note: f1 for pwm modulation clock and f2 for sam - pling clock f0 f sys /(n+1) n=0~7 (n:3 bits preload counter) on the above table, we can easily see that the sampling rate is dependent on the system clock. if start bit is set to 1 , the pwm2 and pwm1 will output a gnd level volt - age. label bits function pwm dis/en 0 enable/disable pwm output 0: enable, 1: disable bz/sp 1 output driver select 1:buzzer ; 0:speaker 6/7 bits 2 pwm counter bit select 1:7 bits ; 0:6 bits p0~p2 3~5 3 bits preload counter bit543: 000b~111b (0~7) bit3: lsb d0, d1 6, 7 pwmi pwmc register d1 d0 pwm interrupt 001 012 104 118 the ratio of latch to interrupt bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 7-bit d7 d6 d5 d4 d3 d2 d1 d0 6-bit d7 d6 d5 d4 d3 d2 d1 x pwm data buffer note: x stands for don t care bit7: sign bit serial i/o interface function the serial interface of the HTG2190 has two types of op - eration mode: master mode and slave mode. in the master mode, it uses an internal clock as synchro - nous clock. in the slave mode, the synchronous output from the external (master side) serial device is input. the master mode and slave mode are selected through registers serc.2 and serc.3; when the master mode is selected, a synchronous clock may be selected from among 2 types as shown in table. serc.3 serc.2 mode synchronous clock 1 1 slave mode external clock 1 0 master mode sclks 0 1 master mode sclkx 0 0 no used 9 , & ( 9 9 . & - & . 3 & - @ " # 4 . @ : ; 7 bits pwm counter bit HTG2190 rev. 1.20 28 july 5, 2002 sout is latch data at h to l by fixed mode serc sclkx sclks b6 b5 b4 0 0 0 16k f sys /4 001 8k f sys /8 010 4k f sys /16 011 2k f sys /32 100 1k f sys /64 1 0 1 512 f sys /128 1 1 0 256 f sys /256 1 1 1 128 f sys /512 at initial reset, the slave mode (external clock mode) is selected. moreover, the synchronous clock, along with the input/output of the 8 bits serial data, is controlled as follows: at master mode, after output of 8 clock from the sclk terminal, clock output is automatically suspended and sclk terminal is fixed at high level. at slave mode, after input of 8 clocks to the terminal, subsequent clock inputs are masked. serial data output by setting the parallel data to serial data registers serdata individually and writing 0 to serc.0, it syn - chronizes with the synchronous clock and serial data is output at the sout terminal. ! & - @ - , & * $ $ & < . 3 : = 1 8 0 & & * 6 $ - c 9 & 0 . 1 : g 6 g , 9 . ' ' & 0 9 , & $ & * j , . & $ & * j i i 27h.1=1 buzzer ! & - @ - , & * $ $ & < . 3 : = 1 & * & & * 6 $ - c , & $ & 4 . & ' 9 & 0 . 1 : g 6 g , 9 . ' ' 9 i i , . & $ & 4 . & ' 27h.1=0 speaker " ' & - " ' * . < = & & " ' * . " ' & - < 0 = & - 6 & ;* use master mode ;* serial clock=f1/2 ;* serial equ 2ah ;serialdatabuffer serc equ 29h ;serial control register data equ 51h ; org 004h jmp serial_op ;serial ; ; serialap: ;serial function testing (pa=16h) mov a,55h mov data,a mov serial,a ;write data to serial register set pbc ;set port b i/p serail_i: clr pbc.5 ;serial clock output mov a,00000111b ;sclkx=f1/2 mov serc,a ;latch data (h->1) wait: sz pb.2 ; jmp wait set eei clr serc.0 ;trigger the serial interface start ret serial_op: mov a,data ;reload data to register mov serial,a clr serc.0 ;enable serial ret HTG2190 rev. 1.20 29 july 5, 2002 when the output of the 8 bits data from d0~d7 is com - pleted, the interrupt factor flag is set to 1 and interrupt is generated. moreover, the interrupt can be masked by the interrupt mask register intc. note, however, that regardless of the setting of the inter - rupt mask register, the interrupt factor flag is set to 1 after output of the 8 bits data. serial data input by writing 0 to serc.0, the serial data is input from the sin terminal, synchronizes with the synchronous clock, and is sequentially read in the 8 bits shift register. the input data will be fetched at the rising edge (.1= 0 ) of sclk. when the input of the 8 bits data from d0~d7 is completed, the interrupt factor flag eif is set to 1 and interrupt is generated. moreover, the interrupt can be masked by the interrupt mask register serdata. note, however, that regardless of the setting of the inter - rupt mask register, the interrupt factor flag is set to 1 after input of the 8 bits data. ;* use slave mode ;* serial clock=external clock ;* org 004h jmp serial_ip ;serial interrupt ; serialap: ;serial function testing (pa=16h) clr pac ;set port a o/p mov a,serial ;show initial data from serial buffer mov pa,a serial_i: set pbc.5 ;serial clock input set serc.2 set serc.3 ;select salve mode set serc.1 ;latch data (h->1) clr serc.0 ;enable trigger clr pbc.2 ;set pb.2 output pin set eei set pb.2 wait: sz pb.2 ; jmp wait mov a,data ;trigger the serial interface start mov pa,a ;show register data to port a ret serial_ip: mov a,serial mov data,a clr pb.2 reti HTG2190 rev. 1.20 30 july 5, 2002 HTG2190 rev. 1.20 31 july 5, 2002 " ' 5 & e " ' 5 & e " ' 1 * * * . * 4 * ) * / * + * 1 d & h & * 2 * 1 & & 3 & 0 & & & & & & & & & & h h & # & - & & $ & $ & : & 0 & & " c & 0 g * * * . * 4 * ) * / * + * 1 * * * . * 4 * ) * / * + * 1 * * * . * 4 * ) * / * + * 1 * * * . * 4 * ) * / * + * 1 * . * . serial data * 1 2 * & & * $ $ 2 1 * i - @ - - @ - & - 4 8 0 - & & & & 4 9 " ' " ' 1 serial i/o HTG2190 rev. 1.20 32 july 5, 2002 the audio output the HTG2190 series provide a 12-bits current type dac devices for driving an external 8 speaker through an external npn transistor. the programmer must write the voice data to the register dal (30h) and dah (31h). only 12 bits which include the high nibble of dal and the whole byte of dah are used. the correct procedure for dac output as shown below, high nibble data of dal must be written next at first, and then the dah data is written. there are 16 scales of volume controllable level that are provided for the current type dac output. the program - mer only writes the volume control data to the volc register (32h). only the high nibble of volc are used. note that writing 0h to the high nibble of volc does not denote mute output, this means there is still leakage from aud pin through external npn transistor, and also external 8 speaker leak current. only load 00h to dah-dal will turn off dac and prevent leakage. : < 2 1 = " < ) 2 1 = " < ) 2 1 = 2 4 2 & * mask option the following shows many kinds of mask options in the HTG2190. all these option should be defined on order to en - sure proper system functioning. no. mask option 1 wdt enable or disable selection. wdt can be enable or disable by mask option. 2 wake-up selection. this option defines the wake-up function activity. external i/o pins (pa only) all have the capability to wake-up the chip from a halt mode by a following edge. 3 external interrupt input pin share with other function selection. int /seg37: int can be set as an external interrupt input pin or lcd segment output pin. 4 i/o pins share with other functions selection. pb0/pwm1: pb0 can be set as i/o pin or positive audio pwm output pin. pwm2/aud: pwm2 can be set as negative pwm output pin or current type d/a output pin. pb4/sout: pb4 can be set as i/o pin or serial data output pin. pb5/sclk: pb5 can be set as i/o pin or serial driving clock pin. pb6/tmr1/rtf: pb6 can be set as i/o pin, timer/event counter 1 input pin or resistor to frequency input pin. pb7/tmr0: pb7 can be set as i/o pin or timer/event counter 0 input pin. 5 i/o pins share with other function selection. pc0/seg56, pc1/seg57, pc2/seg58, pc3/seg59, pc4/seg60, pc5/seg61: pc0~pc5 can be set as i/o pins or lcd segment output pins. pc6/seg63/xin, pc7/seg62/xout: pc6, pc7 can be set as i/o pins, lcd segment output pins or xin, xout pins are connect to 32768hz crystal. 6 segment output pins share with other function selection. seg55~seg48/pd7~pd0: seg55~seg48 can be set as lcd segment output pins or i/o pins. seg47~seg40/pe7~pe0: seg47~seg40 can be set as lcd segment output pins or i/o pins 7 lcd common selection. there are two types of selection: 8-common or 16-common 8 lcd type selection. there are two types of selection: black/white lcd or color ecb application circuits note: * optional capacitors can be added to get a more accurate frequency. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate value of external capacitors. ** r=100k ,f sys =2mhz r=200k ,f sys =1mhz HTG2190 rev. 1.20 33 july 5, 2002 2 1 ( + 4 ( 1 ( + . ( + ( 2 / 2 + 4 < > g = " " , ( * , . ( * / ( " ' * ) ( * . * 4 * + ( * 1 ( . . . 4 4 ) ) 4 ) 2 1 ( + 4 ( 1 ( + . ( + ( " " , . ( * / ( " ' * ) ( * . * 4 * + ( * 1 ( . . . 4 4 ) ) 4 ) 3 ' 3 / 4 . & ' & * ; ; 2 / 2 + 4 < > g = ! " # # $ $ h h + . @ < $ % e ) : ; = h h + . @ < $ % e ) : ; = g 9 4 @ 4 @ . . 9 g 9 g 9 g 9 g 9 g 9 g 9 g 9 g 9 g 9 g 9 g 9 g 9 g 9 . @ 4 @ 4 @ . . 9 g 9 instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none HTG2190 rev. 1.20 34 july 5, 2002 mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pd to (4) ,pd (4) to (4) ,pd (4) none none to,pd note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address : flag is affected : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to and pd are cleared. otherwise the to and pd flags remain unchanged. HTG2190 rev. 1.20 35 july 5, 2002 instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) tc2 tc1 to pd ov z ac c addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c HTG2190 rev. 1.20 36 july 5, 2002 and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) tc2 tc1 to pd ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack pc+1 pc addr affected flag(s) tc2 tc1 to pd ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m] 00h affected flag(s) tc2 tc1 to pd ov z ac c HTG2190 rev. 1.20 37 july 5, 2002 clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) tc2 tc1 to pd ov z ac c clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pd) and time-out bit (to) are cleared. operation wdt 00h pd and to 0 affected flag(s) tc2 tc1 to pd ov z ac c 00 clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pd and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pd flags remain unchanged. operation wdt 00h* pd and to 0* affected flag(s) tc2 tc1 to pd ov z ac c 0* 0* clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pd and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the to and pd flags remain unchanged. operation wdt 00h* pd and to 0* affected flag(s) tc2 tc1 to pd ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m] [m ] affected flag(s) tc2 tc1 to pd ov z ac c HTG2190 rev. 1.20 38 july 5, 2002 cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m ] affected flag(s) tc2 tc1 to pd ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0 (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0 (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4 acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4 acc.7~acc.4+ac1,c=c affected flag(s) tc2 tc1 to pd ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) tc2 tc1 to pd ov z ac c deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) tc2 tc1 to pd ov z ac c HTG2190 rev. 1.20 39 july 5, 2002 halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pd) is set and the wdt time-out bit (to) is cleared. operation pc pc+1 pd 1 to 0 affected flag(s) tc2 tc1 to pd ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m] [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation pc addr affected flag(s) tc2 tc1 to pd ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) tc2 tc1 to pd ov z ac c HTG2190 rev. 1.20 40 july 5, 2002 mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) tc2 tc1 to pd ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m] acc affected flag(s) tc2 tc1 to pd ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation pc pc+1 affected flag(s) tc2 tc1 to pd ov z ac c or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) tc2 tc1 to pd ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c HTG2190 rev. 1.20 41 july 5, 2002 ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation pc stack affected flag(s) tc2 tc1 to pd ov z ac c ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation pc stack acc x affected flag(s) tc2 tc1 to pd ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation pc stack emi 1 affected flag(s) tc2 tc1 to pd ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 [m].7 affected flag(s) tc2 tc1 to pd ov z ac c HTG2190 rev. 1.20 42 july 5, 2002 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 c c [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 c c [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 affected flag(s) tc2 tc1 to pd ov z ac c rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 [m].0 affected flag(s) tc2 tc1 to pd ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 c c [m].0 affected flag(s) tc2 tc1 to pd ov z ac c HTG2190 rev. 1.20 43 july 5, 2002 rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 c c [m].0 affected flag(s) tc2 tc1 to pd ov z ac c sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+c affected flag(s) tc2 tc1 to pd ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) tc2 tc1 to pd ov z ac c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) tc2 tc1 to pd ov z ac c sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) tc2 tc1 to pd ov z ac c HTG2190 rev. 1.20 44 july 5, 2002 set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) tc2 tc1 to pd ov z ac c set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) tc2 tc1 to pd ov z ac c siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i 0 affected flag(s) tc2 tc1 to pd ov z ac c HTG2190 rev. 1.20 45 july 5, 2002 sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) tc2 tc1 to pd ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+1 affected flag(s) tc2 tc1 to pd ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) tc2 tc1 to pd ov z ac c swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) tc2 tc1 to pd ov z ac c swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) tc2 tc1 to pd ov z ac c HTG2190 rev. 1.20 46 july 5, 2002 sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) tc2 tc1 to pd ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c HTG2190 rev. 1.20 47 july 5, 2002 xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m] acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op - eration. the result is stored in the accumulator. the 0 flag is affected. operation acc acc xor x affected flag(s) tc2 tc1 to pd ov z ac c HTG2190 rev. 1.20 48 july 5, 2002 package information 128-pin qfp (14 20) outline dimensions symbol dimensions in mm min. nom. max. a 17.00 17.50 b 13.90 14.10 c 23.00 23.50 d 19.90 20.10 e 0.50 f 0.20 g 2.50 3.10 h 3.40 i 0.10 j 0.65 0.95 k 0.10 0.20 0 7 HTG2190 rev. 1.20 49 july 5, 2002 HTG2190 rev. 1.20 50 july 5, 2002 copyright 200 2 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5/f, unit a, productivity building, cross of science m 3rd road and gaoxin m 2nd road, science park, nanshan district, shenzhen, china 518057 tel: 0755-8616-9908, 8616-9308 fax: 0755-8616-9533 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 010-6641-0030, 6641-7751, 6641-7752 fax: 010-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 028-6653-6590 fax: 028-6653-6591 holmate semiconductor, inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com |
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